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By G. Russell, I.L. Sayers

Publication by way of Russell, G., Sayers, I.L.

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Extra resources for Advanced Simulation and Test Methodologies for VLSI Design

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The implementation of on-chip DfD instrumentation varies from one SoC design to another. There have been industrial efforts to establish standards for common DfD components that can be reused across different SoC implementations. These efforts result in several popular hardware debug architectures and ecosystems, such as Nexus and ARM Coresight, which standardize the DfD components and their communication protocols. We will take the ARM Coresight Debug Architecture as an example to illustrate DfD components commonly implemented in today’s SoC debug architecture.

Correctness and security at odds: post-silicon validation of modern SoC designs. In: Proceedings of the 52nd Annual Design Automation Conference (2015) 12. Homebrew Development Wiki: JTAG-Hack. com/wiki/JTAG-Hack 13. : Smart nest thermostat: a smart spy in your home. In: Black Hat USA (2014) 14. : Critical timing analysis in microprocessors using near-IR laser assisted device alteration (LADA). In: IEEE International Test Conference, pp. 264–273 (2003) 15. com/ 16. : MERO: A statistical approach for hardware trojan detection.

Scan attacks and countermeasures in presence of scan response compactors. In: European Test Symposium (ETS), 2011 16th IEEE, pp. 19–24 (2011) 17. Dishnet: In house made with locking script. htm (2012) 18. : Differential scan attack on AES with x-tolerant and x-masked test response compactor. In: 2012 15th Euromicro Conference on Digital System Design (DSD), pp. 545–552 (2012) 19. Freescale: Introduction to HCS08 background debug mode (2006) 20. mx 6solox applications processor reference manual (2014) 21.

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